The recent FMS 2026 conference in Santa Clara, once organized around flash storage, now functions as an AI memory-and-data-infrastructure conference, confirming a shift that has been building over several product cycles. It’s no wonder the event changed its name from “Flash Memory Summit” to “Future of Memory and Storage.”

NVIDIA, Samsung, SK hynix, Kioxia, SanDisk, Micron, Marvell, and a wave of smaller vendors used the show to present NAND, CXL-attached memory, and specialized flash as active components of the AI accelerator’s memory hierarchy.

The traditional pipeline from GPU HBM to system DRAM to SSD to capacity storage is fragmenting into a far more layered structure built around inference economics, KV-cache placement, and the cost of keeping GPUs fed with data.

Here, inference economics means optimizing cost per token, useful work per watt, GPU utilization, memory capacity, and data-movement overhead across the system.

What we saw at FMS was a push to move fewer bytes over shorter distances, place data closer to compute, and pool expensive resources rather than duplicating them.

The Announcements & Themes That Mattered Most

There were seven developments from the show floor that carry the greatest weight for buyers and competitors alike:

• Expanding Storage-Next: NVIDIA introduced SCADA, open-sourced cuFile, and expanded Storage-Next to more than 40 participants, as part of an effort to establish a common model for GPU-initiated storage access.
• High Bandwidth Flash (HBF): SK hynix and SanDisk released the first OCP HBF specification, backed by Google and Tenstorrent, to form a tier between HBM and SSDs.
• GPU-Adjacent Flash: Kioxia introduced the XL-FLASH and the PCIe 6.0-based GP1 Series as GPU-adjacent memory extensions; both won FMS’s Specialized Storage Best of Show award.
• Architectural Concept Cars: Samsung previewed zHBM and zNAND-O alongside V10 BV-NAND, pointing toward vertically stacked memory and shorter data paths.
• PCIe 6.0 SSDs Shipping: Micron’s 9650, the first PCIe 6.0 enterprise SSD in mass production, moved the interface from roadmap discussion to deployment.
• CXL Memory Pooling: Marvell and XCENA presented CXL memory-pooling approaches for shared, composable AI memory.
• Increasing Capacity: Kioxia, SanDisk, and Samsung advanced 332- to 400-plus-layer NAND, while DapuStor showcased a 512TB SSD.

Let’s take a look at what each contributes to the emerging hierarchy.

Storage Joins the AI Memory Hierarchy

Three forces are pulling storage into territory once reserved for DRAM:

• Model context windows and KV-cache requirements now exceed what data centers can economically provision in HBM or DRAM alone.
• Agentic inference generates enormous volumes of small, random data accesses.
• GPU utilization keeps expensive GPU clusters busy, increasingly dependent on delivering the right data with minimal latency, energy, and software overhead.

Together, they’re shifting the storage conversation beyond aggregate throughput toward small-block IOPS, 512-byte operations, GPU-direct access, and cost per useful token.

NVIDIA pushed this argument hardest. The company formally introduced SCADA, which has nothing to do with industrial control systems. Instead, Scaled Accelerated Data Access is a framework that allows GPUs to initiate and manage storage I/O directly, rather than routing every request through a CPU and filesystem stack.

The company also paired the announcement with the open-sourcing of cuFile through XIO-SIG, with Google, Intel, Meta, and NVIDIA as founding maintainers.

It also announced the expansion of Storage-Next, an initiative that now covers more than 40 storage, flash, and controller vendors, including DDN, Kioxia, and Micron. 

NVIDIA’s SCADA collapses the conventional path of GPU to CPU to filesystem to SSD into something closer to GPU-to-storage directly, with the accelerator managing more of the I/O.

Micron provided the most compelling proof point, running SCADA across 44 Micron 9650 PCIe Gen6 SSDs behind three Broadcom PEX90000 switches, driven by three NVIDIA H100 GPUs, achieving roughly 230 million 512-byte IOPS from a single server.

It’s a figure that matters because embeddings, vector retrieval, and KV-cache lookups generate transactions at this scale.

It’s clear that NVIDIA views storage architecture as critical to the evolution of scalable, high-performance AI clusters and is striving to secure a leadership position. While many component suppliers are on board, we’re still waiting to see broader adoption across storage systems, controllers, and software. 

Regardless, vendors already have a reason to optimize for both GPU access patterns and server bandwidth.

Where this leaves the non-NVIDIA ecosystem is something to continue to watch.

PCIe 6.0 Becomes Deployable Infrastructure

PCIe 6.0 moved from roadmap to shipping product at FMS 2026:

• Micron‘s 9650 entered mass production in February 2026 and is the first commercial PCIe 6.0 enterprise SSD, doubling the interface bandwidth of PCIe 5.0 SSDs and delivering roughly 28 GB/s and 5.5 million IOPS, with support for air and liquid cooling. 
• Kioxia‘s CM10 followed as its first PCIe 6.0 enterprise drive
• Marvell showed its own PCIe 6.0 enterprise SSD controller, the Bravera SC6, alongside its broader portfolio.

PCIe 6.0 matters because AI infrastructure is simultaneously scaling SSD throughput, accelerator bandwidth, memory expansion, DPU traffic, CXL traffic, and accelerator-to-storage communication, and PCIe now serves as the common fabric tying them all together.

Flash Vendors Building NAND for GPUs, Not Servers

Kioxia offered the clearest example of NAND purpose-built for accelerators. Its new GP1 Series, built on second-generation XL-FLASH and PCIe 6.0, delivers up to 10 million random-read IOPS per SSD.

Its second launch, the CM10, became the company’s first PCIe 6.0 enterprise SSD, built around:

• NVMe 2.1 paired with 332-layer BiCS10 TLC NAND
• Capacities spanning 1.6TB to 61.44TB
• E3.S, E1.S and 2.5-inch form factors
• Support for NVIDIA’s CMX and KV-cache applications
• Liquid-cooling support on select form factors

The broader story is that flash is splitting into distinct classes engineered for different rungs of the AI memory-and-storage hierarchy, from GP1’s accelerator-adjacent role to CM10’s role as high-capacity enterprise infrastructure.

Two Vision for HBF

The most contested new category at FMS 2026 was High-Bandwidth Flash, flash engineered to sit physically and architecturally between HBM and conventional SSDs.

SK hynix and SanDisk released the first open HBF specification through the Open Compute Project, building on the consortium they launched with Google and Tenstorrent earlier this year.

The initial specification calls for capacities up to 512GB and bandwidth approaching 3TB/s over UCIe connectivity, applying to NAND large die counts, wide interfaces and close physical proximity to compute.

Samsung, however, is taking a different path. The company is pursuing zHBM, a concept that stacks HBM directly on top of the accelerator rather than beside the processor, thereby shortening the data path and targeting lower power draw and reduced thermal resistance.

The category carries a caution. In the proactively titled research paper, HBF Sucks! A Full-Stack Characterization of High-Bandwidth Flash for KV-Centric LLM Serving, published by Chinese researchers immediately after FMS claims that simply substituting HBF for SSDs in KV-cache architectures does not automatically improve system performance; workload placement, write intensity, thermal behavior, and the amount of HBM sacrificed to make room for the new tier all affect the outcome.

The paper reinforces the theme that ran throughout the entire show: namely, that the AI memory hierarchy needs software and workload awareness, not just faster media.

We expect this will shake out over the coming quarters.

The Density Race Enters a New Phase

Even as bandwidth-focused tiers multiply, AI infrastructure still needs enormous, inexpensive capacity behind the accelerator, and the three largest NAND makers used FMS to press their density stories:

• Samsung introduced V10 BV-NAND, the industry’s first NAND product with more than 400 layers, using wafer bonding to stack cells and lifting density by roughly 58% over the prior V9 generation. Samsung paired the launch with previews of zNAND-O, a wafer-bonding approach that bonds NAND over logic to increase bandwidth while reducing data movement, latency, and power, alongside its zHBM concept.
• SK hynix countered with its 10th-generation, 375-layer 4D NAND, which was shown publicly on the exhibition floor for the first time and claimed a 2.5x improvement in power efficiency over the prior generation.
• Kioxia and SanDisk pushed the BiCS10 NAND behind the GP1 and CM10 products even further, reaching more than 37Gb/mm² areal density in QLC and 29Gb/mm² in TLC at 332 layers, with interface speeds up to 4,800 MT/s, edging out Samsung’s per-layer density claims despite a lower layer count.

CXL Pooling Targets the Capacity Gap Behind the GPU

CXL remained a major theme at FMS, and inference provides a clearer reason for the technology’s growing strategic importance.

KV cache turns memory capacity into a scaling constraint, where one host can exhaust local memory while another leaves capacity idle.

When memory remains tied to individual systems, clusters compensate by overprovisioning or reducing utilization. Pooling can convert that stranded capacity into a shared resource, improving the economics of long-context and multi-session inference. 

The discussion at FMS naturally focused on shared memory, tiering, and composable AI infrastructure rather than on simple DRAM expansion.

Marvell presented the broadest CXL portfolio update, spanning near-memory acceleration, memory expansion, memory compression, CXL switching, and expansion cards. Its Structera S 30260 CXL switch is the most direct expression of that portfolio:

• Pools 48TB of memory across 16 or 32 hosts
• Delivers 4TB/s of aggregate bandwidth
• Holds round-trip latency under 460 nanoseconds

That puts Marvell in direct competition with Astera Labs’ Leo controllers, CXL switch vendor XConn, and expander-controller supplier Montage Technology for the same hyperscaler accounts.

XCENA went further, unveiling its MX1 production lineup with a CXL memory pool up to 20TB and a KV-cache-sharing architecture that lets multiple inference servers draw on shared memory resources.

These approaches remain at different stages of ecosystem maturity, but the ultimate goal is pooling KV cache and inference memory to reduce stranded capacity and improve GPU utilization without adding another GPU.

Bottom Line: What FMS 2026 Means for 2027 Buyers

FMS 2026 saw the storage industry shift its AI narrative. During the training-centric phase of AI infrastructure, storage played a supporting role by feeding checkpoints and training data to GPU clusters.

Inference expands the problem. Long context, KV cache, retrieval-augmented generation, embeddings, and agentic workloads require a layered hierarchy spanning HBM, DRAM, pooled CXL memory, high-bandwidth flash, high-IOPS SSDs, and capacity flash. 

In inference-heavy environments, 512-byte random IOPS, accelerator-direct access, KV-cache behavior, CXL support, power efficiency, and dynamic data placement increasingly matter alongside conventional bandwidth.

Buyers should also separate what can be deployed now from emerging specifications and from longer-term architectural concepts.

AI infrastructure decisions heading into 2027 will determine which parts of this hierarchy become locked to platforms, software stacks, and vendor ecosystems, creating architecture choices with real lock-in risk.