At Hot Chips 2026, IBM disclosed the next-generation processor for its Z and LinuxONE systems, the first commercial chip designed to execute both IBM’s z/Architecture and Arm instruction sets natively on the same physical cores. 

IBM and Arm first announced their partnership in April 2026 but provided little detail.  This announcement marks the first processor-level output of the collaboration. IBM has not given the chip an official product name, but we expect it will be called Telum III, consistent with the naming convention of its two predecessors.

The processor addresses a problem that has constrained mainframe adoption for years. IBM Z delivers transaction processing reliability and consolidation economics that x86 fleets do not match on a like-for-like basis, but the software ecosystem built around the platform’s s390x instruction set remains a fraction of the size of the ecosystems for x86 and Arm.

By adding full hardware support for AArch64 alongside z/Architecture, IBM is enabling ISVs already building for Arm to bring their tools to the mainframe without a separate porting effort. This promises to be a significant enabler for LinuxONE in particular.

Technical Details

IBM’s presentation at Hot Chips 2026 detailed a processor design that integrates Arm’s AArch64 instruction set directly into the same physical cores that execute IBM’s z/Architecture instructions, rather than taking the easier path of adding separate Arm cores or relying on emulation.

IBM is reusing existing z/Architecture microarchitectural components, including branch prediction, address translation, and arithmetic execution paths, and adding new control logic, system registers, and endianness-handling circuitry to support Arm’s little-endian data model alongside z/Architecture’s big-endian model.

The chip pairs this dual-ISA core design with an updated AI acceleration stack spanning on-chip inference, a PCIe-attached accelerator card, and a dedicated I/O processing unit.

Key details include:

• Manufactured on a 2-nanometer process node with 11 high-performance cores per chip, each running at a sustained base clock above 5.7 GHz without boost or turbo mode, IBM describes it as the fastest commercially available enterprise processor operating continuously at its stated clock speed.
• Each core implements simultaneous multithreading with two threads per core and includes 36MB of private L2 cache. IBM’s cache-pooling scheme extends this to virtual 432MB L3 and 3.5GB L4 caches shared across cores.
• Arm support is implemented in full hardware rather than in emulation, covering AArch64 version 9.3 with the SVE and SVE2 vector extensions and 2,792 distinct AArch64 instructions. IBM said that each core switches between z/Architecture and Arm execution with effectively “zero performance penalty” because the switching overhead amortizes over multi-millisecond workload windows.
• The processor includes a dedicated on-chip Data Processing Unit for I/O acceleration, network traffic handling, and cryptographic offload, as well as separate hardware blocks for compression and sorting.
• A second-generation on-chip AI accelerator handles real-time inference during transaction processing, complemented by a new PCIe-attached AI accelerator card, the successor to IBM’s Spyre card, which provides 16 active AI cores plus one redundant core, support for FP4 and MXFP4 datatypes, up to 4x the TOPS throughput of the prior generation, 96GB of HBM3e memory with approximately 4TB/s of bandwidth, and PCIe Gen6 connectivity.
• Systems built on the new processor will scale to hundreds of cores and tens of terabytes of memory, with a reliability target of eight nines of availability, equivalent to roughly 0.3 seconds of unplanned downtime per year.
• Arm workloads run as guest partitions under KVM and Red Hat OpenShift virtualization. IBM’s z/VM hypervisor, which manages the bulk of existing Z virtualization environments, is not part of the Arm execution path in this generation.

Analysis

The announcement extends IBM’s long-running argument that the mainframe should be evaluated as consolidated infrastructure. Native Arm execution is IBM’s move to close the software availability gap that has limited how much workload enterprises are willing to move onto Z hardware, by aligning the platform with an instruction set that a much larger population of developers and independent software vendors already targets.

Practitioner Impact

For IBM Z and LinuxONE customers, the practical change is that Linux and containerized workloads built for Arm can now run inside the same physical footprint as z/OS transaction processing, using the mainframe’s existing partition isolation and internal low-latency networking to reach system-of-record data without crossing an external network.

That proximity is the core operational benefit IBM is selling, since it removes a network hop and the associated security exposure for workloads such as fraud scoring, monitoring agents, and AI inference that need to sit close to transactional data.

Competitive Impact

The new processor competes less with other mainframe vendors, since IBM has no direct mainframe competitor at meaningful scale, than with the broader set of platforms enterprises already use to run Arm and Linux workloads.

That set includes hyperscaler-built Arm server silicon, standalone Arm CPU vendors, Arm-based AI infrastructure, and the x86 server fleets IBM’s consolidation pitch has always targeted.

IBM’s differentiation is strongest against x86 and hyperscaler Arm alternatives on reliability and data proximity, characteristics rooted in decades of mainframe engineering that competitors have not replicated.

Final Thoughts

IBM described a substantial piece of silicon engineering at Hot Chips. Implementing AArch64 in full hardware within the same cores that execute z/Architecture, while preserving z/Architecture’s reliability characteristics, is a harder problem than adding a co-processor or an emulation layer.

What remains unresolved is everything beyond the chip itself. IBM has not published Arm-side performance data, has not named independent software vendors committed to shipping on the platform, has not clarified per-core licensing for Arm workloads, and has excluded z/VM from the initial virtualization path, a move that will require existing Z shops to adopt new operational tooling.

Those gaps are typical for a Hot Chips disclosure, well ahead of general availability, expected in the 2027 to 2028 window. But they are also exactly the variables that determine whether the mainframe’s software ecosystem widens, or whether Arm support becomes a capability that enterprises rarely use.

The announcement ultimately matters because it changes the terms under which IT leaders can evaluate mainframe consolidation. A mainframe that can run Arm-native Linux and AI workloads alongside z/OS, within the same partition boundary and without a separate porting effort, is a materially different infrastructure decision than one that requires custom s390x ports for every tool an enterprise wants close to its transaction data.

The architecture IBM showed at Hot Chips removes the technical excuse that kept many of those workloads off the platform in the first place.