While the focus of CES 2026 remained on consumer electronics, this year felt different. More expansive, with the semiconductor industry dominating the pre-show with overlapping announcements that reveal diverging strategies for AI workload acceleration, manufacturing sovereignty, and market expansion beyond traditional computing segments.

AMD, Intel, NVIDIA, and Qualcomm each used the Las Vegas event to stake positions across data center infrastructure, client computing, and emerging physical AI applications, while navigating supply chain constraints that threaten to limit 2026 product availability.

Let’s look at what each announced.

NVIDIA Stakes Rubin Platform on Inference Economics

In an overflowing event, NVIDIA used its CES keynote to launch the Vera Rubin platform. CEO Jensen Huang confirmed full production status for all six chips comprising the platform, with cloud deployment beginning in the second half of 2026 through AWS, Google Cloud, Microsoft Azure, and Oracle Cloud Infrastructure.

The Rubin platform comprises six interconnected chips that NVIDIA describes as “extreme codesign” for AI supercomputing:

• Vera CPU: 88 Arm-based “Olympus” cores with spatial multithreading support, 2 MB L2 cache per core (double Grace CPU’s allocation), and 162 MB shared L3 cache across all cores
• Rubin GPU: 336 billion transistors fabricated on TSMC’s N3 process, containing the primary AI compute resources
• NVLink 6 switch: Provides 3.6 TB/s bidirectional bandwidth per GPU for dense scale-up configurations
• ConnectX-9 SuperNIC: Delivers up to 1.6 Tb/s per GPU with PCIe Gen6 switching
• BlueField-4 DPU: Handles data processing and security functions within the rack
• Spectrum-6 Ethernet switch: Manages scale-out networking with co-packaged optics offering 5x power efficiency and 10x reliability versus traditional switches

Targeting Inference Workloads

The Rubin GPU delivers performance metrics specifically optimized for inference rather than training workloads:

• Inference: 50 PFLOPS using NVFP4 data type (5x Blackwell GB200)
• Training: 35 PFLOPS with NVFP4 precision (3.5x Blackwell’s 10 PFLOPS)
• Memory: Eight HBM4 stacks providing 288GB capacity and 22 TB/s bandwidth (2.75x improvement over Blackwell’s 8 TB/s from HBM3E stacks)
• Cost reduction: 10x reduction in cost per inference token compared to Blackwell systems

NVIDIA said that these specifications address a fundamental shift in AI deployment patterns, with enterprises now run AI systems primarily for inference rather than training. This changes the infrastructure requirements from peak training throughput to sustained inference efficiency, memory bandwidth, and context management.

Rack-Scale System Architecture

The Vera Rubin NVL72 rack-scale system integrates 72 GPUs (144 GPU dies) alongside 36 Vera CPUs in a fully liquid-cooled configuration that eliminates traditional air-cooling infrastructure. NVIDIA engineered several operational improvements:

• Cable-free modular GPU trays supporting field upgrades without system downtime
• 130kW power densities per rack enabled by liquid cooling
• Installation time reduced by half compared to previous generations
• Total system bandwidth NVIDIA claims exceeds “the entire internet”

Inference Context Memory Storage Platform

NVIDIA simultaneously announced its Inference Context Memory Storage platform, introducing an additional memory tier between GPU memory and traditional storage.

The company claims 5x improvements in throughput and power efficiency for context-heavy inference workloads, addressing the growing cost and inefficiency of maintaining large KV caches in agentic AI systems.

Autonomous Vehicles and Physical AI

If CES is increasingly about core technologies, it’s also very much focused on automotive and mobility, with the entire LVCC West space dedicated to it.

Aligning with this focus, NVIDIA also announced Alpamayo, an open portfolio of reasoning vision-language-action models for autonomous vehicle development:

• Alpamayo R1: First open reasoning VLA model for autonomous driving
• AlpaSim: Fully open simulation blueprint for high-fidelity AV testing
• Cosmos: World foundation models trained on video, robotics data, and simulation for creating synthetic training environments

Jensen, in his keynote, emphasized its full-stack approach to physical AI, integrating foundation models, simulation tools, and edge computing through its robotics ecosystem.

AMD Targets Data Center Density

AMD CEO Lisa Su opened CES 2026 with announcements spanning client processors, data center accelerators, and server platforms. The company released details on its Venice server CPU platform and MI400 Series accelerators, both targeting 2026 deployment.

Venice Server Platform Architecture

Venice integrates eight CCDs each containing 32 Zen 6 cores for a total of 256 cores per package fabricated on TSMC’s 2nm process:

Key architectural specifications include:

• CCD size: Approximately 165mm² on N2 silicon
• Core density: Roughly 5mm² per Zen 6 core plus 4MB L3 cache (comparable to Zen 5’s 5.34mm² on N3)
• IO dies: Dual IO dies totaling over 700mm² of silicon (up from approximately 400mm² in previous EPYC generations)
• Packaging: Advanced packaging for both CCDs and IO dies
• Power delivery: Eight additional small dies flanking IO dies likely serving as structural silicon or deep trench capacitors

AMD announced Venice-X, presumably a V-Cache variant, which would mark the first time a high core count CCD supports V-Cache technology.

If AMD maintains its cache ratio of base die to V-Cache die, each 32-core CCD would contain up to 384MB L3 cache, yielding 3GB L3 cache across the chip.

MI400 Series Accelerator Portfolio

The MI400 Series accelerator portfolio targets diverse AI deployment scenarios with three distinct products:

• MI455X: Anchors AMD’s Helios rack-scale architecture, delivering up to 3 AI exaflops in a single rack for trillion-parameter training with maximum bandwidth and efficiency
• MI440X: Targets eight-GPU on-prem solutions for enterprise AI training, fine-tuning, and inference workloads that integrate into existing infrastructure
• MI430X: Provides high-precision GPU capabilities for sovereign AI and HPC hybrid computing

AMD disclosed preliminary MI500 Series specifications for 2027 launch, claiming up to 1,000x AI performance increase versus MI300X through CDNA 6 architecture, 2nm process technology, and HBM4E memory.

This projection assumes continued scaling of both semiconductor process technology and high-bandwidth memory specifications through 2027.

Software Ecosystem Development

AMD introduced ROCm 7.2 software for Windows and Linux with native support for Ryzen AI 400 Series processors and integration into ComfyUI. The company claims 10x year-over-year download growth driven by:

• Doubled platform support across Ryzen and Radeon in 2025
• Expanded availability across Windows and Linux distributions
• Seamless integration with popular AI development workflows

Qualcomm’s New PC Parts + A New Focus on Robotics

Qualcomm announced the Snapdragon X2 Plus at CES 2026, expanding its Windows PC processor portfolio with a mainstream platform:

• Third-generation Oryon CPU cores
• 80 TOPS NPU capability (matching Snapdragon X2 Elite’s AI performance)
• Six-core or 10-core CPU configurations
• Up to 35% faster peak single-core performance versus prior X Plus generation
• 29% GPU performance improvements
• Multi-day battery life claimed

OEM Support and Availability

Qualcomm secured design wins from Acer, ASUS, HP, Lenovo, Microsoft, and Samsung, though the company did not specify how many PC models will launch in 2026 using the X2 Plus chipset. HP’s OmniBook Ultra 14 incorporates X2 Plus alongside Intel Panther Lake options, with an exclusive X2 Plus variant featuring 85 TOPS.

The Snapdragon X2 Plus joins the previously announced X2 Elite and X2 Elite Extreme processors as part of Qualcomm’s push to take on Intel and AMD in the PC market.

Qualcomm Enters Robotics with Dragonwing IQ10

Qualcomm introduced its new Dragonwing IQ10, a comprehensive robotics platform targeting applications from consumer robots through industrial robotics to humanoid systems. T

Platform Architecture

The IQ10 chipset integrates multiple Qualcomm technologies adapted for robotics applications:

• Oryon processor cores: First deployed in Qualcomm’s PC chipsets
• Adreno graphics: Adapted for robotics vision processing
• Spectra image signal processors: Handle camera input and machine vision
• Dedicated robotics silicon: Purpose-built accelerators for robotics-specific workloads

Qualcomm leverages its autonomous driving expertise to address robotics markets, emphasizing full-stack architecture and AI model support.

Ecosystem Partnerships

Qualcomm highlighted ecosystem partnerships including:

• Advantech, Aplux, AutoCore (industrial and automotive robotics)
• Booster, Figure, Kuka Robotics (manufacturing and humanoid robotics)
• Robotec.ai, VinMotion (software and integration)

Analyst’s Take

CES 2026 crystallized fundamentally different approaches to AI infrastructure across the semiconductor industry, with each vendor pursuing distinct strategies based on existing strengths and market positioning.

The four major semiconductor vendors pursue divergent paths to AI infrastructure leadership:

• NVIDIA: Extreme vertical integration with rack-scale systems optimizing every component for AI workloads, from silicon through networking, storage, and software stacks
• AMD: Scale-up density through Helios architecture while maintaining broader HPC compatibility and open software ecosystem via ROCm
• Intel: Manufacturing sovereignty and domestic production through 18A validation, emphasizing process technology leadership and supply chain security
• Qualcomm: Edge-to-cloud diversification across PCs, robotics, and automotive to reduce smartphone concentration and capture emerging physical AI markets

Execution Risk and Timeline Pressure

The 2026 semiconductor landscape will test each vendor’s execution capability under multiple constraints:

Supply chain challenges:

• HBM4 availability and allocation between competing demands
• DDR5 pricing volatility affecting client computing margins
• Co-packaged optics production for high-bandwidth networking

Manufacturing execution:

• Intel 18A yield improvements determining competitive positioning
• AMD MI400 Series ramp meeting hyperscaler deployment schedules
• NVIDIA Rubin production scaling to meet cloud provider commitments

Market timing:

• NVIDIA Rubin availability in second half 2026 sets competitive timeline
• AMD Venice and MI400 deployment windows determine data center market share
• Qualcomm PC adoption rates indicate Arm sustainability against x86 incumbents

The real story at CES 2026 isn’t the chip announcements, but rather the supply chain chokepoint that determines who actually gets to deploy these systems:

NVIDIA launched the most complete AI infrastructure stack, but hyperscalers are hedging with custom silicon because no one wants single-vendor dependence when stakes reach trillions.

AMD plays the open alternative with ROCm, but software ecosystems don’t flip on technical merit alone.

Intel salvaged credibility with 18A validation, but credibility doesn’t win foundry customers without economic competitiveness against TSMC.

At the end of the day (or at least this day), the on-going memory crisis matters more than any chip roadmap. When Samsung warns prices are rising during CES, that’s a signal that 2026 deployment plans exceed available supply by a significant margin.

This creates a two-tier market: hyperscalers with procurement leverage get allocations and deploy at scale, while everyone else (enterprises, research labs, well-funded startups) wait in line or pay punishing premiums.