Quantum computers derive their power from the same quantum-mechanical properties that make them difficult to build: superposition, entanglement, and interference. A qubit can represent zero, one, or both simultaneously, a property that classical bits cannot replicate. Those quantum states, however, are extraordinarily fragile.
Stray electromagnetic fields, temperature fluctuations, and even cosmic radiation can corrupt qubit states through two fundamental error types:
- Bit flips, where a qubit’s state reverses unexpectedly
- Phase flips, where the phase relationship between quantum states shifts in ways that corrupt computation.
The error rate problem is not minor. Physical qubits in today’s best systems still produce errors at rates around 0.1%, and running complex algorithms requires millions or billions of gate operations. At those error frequencies, computation degrades into noise long before producing a useful result.
This is the defining barrier between the noisy intermediate-scale quantum (NISQ) era, in which quantum computers exist but cannot reliably outperform classical systems on practical problems, and the fault-tolerant era, in which quantum computers correct their own errors in real time.
Quantum error correction (QEC) addresses this by encoding a single logical qubit across multiple physical qubits. The logical qubit holds the computation, while the physical qubits redundantly protect it.
By continuously measuring stabilizer operators — quantities that detect errors without revealing or collapsing the underlying quantum information — the system identifies where errors have occurred and applies corrective operations before they propagate.
The technique is conceptually analogous to classical error-correction codes used in data storage and transmission, but the quantum-mechanical constraint that measuring a qubit destroys its state introduces an engineering challenge that has taken decades of theoretical work to resolve.
The threshold theorem, a foundational result in quantum information theory, establishes that if physical error rates fall below a threshold, adding more physical qubits per logical qubit exponentially suppresses the logical error rate. Below threshold, more qubits mean greater reliability. Above threshold, more qubits mean more errors.
The central race in quantum computing today is to operate hardware reliably below that threshold and to do so with enough qubits to encode useful numbers of logical qubits.
QEC Drives the Commercialization Timeline
The practical significance of QEC extends beyond technical elegance. Without it, the most commercially valuable quantum algorithms cannot run at scale. Shor’s algorithm, which threatens modern public-key cryptography, requires fault-tolerant logical qubits to break RSA encryption at practical key sizes. Quantum chemistry simulations capable of discovering new materials or accelerating drug design require circuits far deeper than today’s NISQ hardware can sustain without error accumulation destroying the result.
Error correction is therefore a fundamental prerequisite for hardware maturity.
Riverlane’s 2025 Quantum Error Correction Report found that all major quantum companies now treat QEC as a competitive differentiator. Investment patterns reflect this, with government funding agencies, enterprise technology buyers, and capital market investors increasingly evaluating quantum vendors based on progress in fault tolerance, not raw qubit counts.
The metrics that matter are how many reliable logical qubits a system can maintain, at what error rate, and at what physical-qubit overhead. Those three dimensions together determine when quantum computing transitions from scientific demonstration to commercial infrastructure.
The work published over the past year from Microsoft, Quantinuum, and IBM marks the first time the field has produced experimental data that constrains those dimensions with engineering precision.
Let’s look at each.
Microsoft and Quantinuum: Peer-Reviewed Validation at Scale
In June, Microsoft and Quantinuum published peer-reviewed results in Nature, providing independent scientific validation of results first announced in April 2024 and extended through 2025.
- The core finding: logical error-rate improvements ranging from 11x to 800x relative to physical-qubit circuit baselines, achieved by running Microsoft’s qubit-virtualization platform on Quantinuum’s trapped-ion Quantum Charge-Coupled Device (QCCD) hardware.
The 800x improvement figure is the largest gap between physical and logical error rates that has been independently validated in the peer-reviewed literature to date.
That scale matters because the benefits of QEC compound. A system that achieves high suppression ratios on small circuits is on track to maintain suppression as circuit depth increases. The 11x figure is equally meaningful, representing the minimum improvement across a range of nontrivial circuit types.
The Underlying Architecture
The Microsoft-Quantinuum collaboration joins two distinct technical approaches. Quantinuum’s H2 hardware uses trapped-ion technology, where individual ions held in electromagnetic traps serve as qubits.
Trapped-ion systems offer all-to-all qubit connectivity, allowing any qubit to interact directly with any other, and achieve two-qubit gate fidelity of 99.921%. That level of fidelity places the hardware below the fault-tolerance threshold for a range of error-correcting codes.
Microsoft contributes the qubit-virtualization and error correction software layer. The qubit-virtualization system executes active syndrome extraction, a process that measures the stabilizer operators identifying errors without measuring (and therefore collapsing) the logical qubit state itself.
The system performs multiple rounds of syndrome extraction, applies classical decoding to interpret the syndrome measurements, and feeds correction operations back to the hardware in real time.
Earlier Microsoft-Quantinuum demonstrations ran more than 14,000 individual experiments without a single observable error, establishing that the architecture can sustain error-free operation over extended experimental runs.
The progression from that initial demonstration to the Nature-published results is significant. While the 2024 demonstration focused on sustained error-free operation in individual experiments, the 2026 publication demonstrates fault-tolerant computation in multi-qubit logical circuits.
The teams demonstrated 12 entangled logical qubits with a circuit error rate near 0.0011, roughly one error per 1,000 operations, approximately 22 times better than the underlying physical qubit performance.
They further demonstrated a hybrid chemistry simulation that combines those logical qubits with AI and high-performance computing to estimate the ground-state energy of a catalytic intermediate to chemical-accuracy precision.
Quantinuum’s Independent QEC Progress
Separate from the Microsoft collaboration, Quantinuum’s research team has substantially increased logical qubit counts. In March 2026, Quantinuum researchers demonstrated quantum computations using up to 94 protected logical qubits on a trapped-ion processor, leveraging iceberg error-correcting codes rather than the more common surface codes.
Logical gate error rates in that demonstration reached about one error per 10,000 operations, substantially lower than the processor’s raw hardware gate errors. The team ran benchmark tests, including large entangled states and a simulation of a quantum magnetic system, demonstrating that error-protected qubit counts now reach operationally useful scales for certain problem classes.
Quantinuum’s current-generation Helios system is designed to sustain at least 10 highly reliable logical qubits below the threshold across a broader set of error-correcting codes. The progression from H2 to Helios is a hardware-scaling path that shows IBM improving both the physical qubit count and gate fidelity to expand the surface over which error correction provides a net benefit.
IBM’s qLDPC Architecture: A Different Path to Fault Tolerance
IBM has made what may prove the most consequential architectural bet in quantum error correction by abandoning surface codes (the dominant approach for superconducting qubit systems) in favor of quantum low-density parity-check (qLDPC) codes, specifically a family IBM calls bivariate bicycle codes.
This pivot crystallized in 2024 when IBM published foundational results in Nature establishing that bivariate bicycle codes deliver error correction comparable to surface codes while requiring roughly 10 times fewer physical qubits to encode the same number of logical qubits.
The efficiency difference is not marginal. Surface codes require approximately 1,000 physical qubits to produce a single high-quality logical qubit at the error rates achievable with current hardware.
IBM’s gross code, the bivariate bicycle implementation at distance 12, encodes 12 logical qubits into 144 data qubits and 144 syndrome-check qubits, yielding 288 physical qubits in total.
That 10x overhead reduction, if it holds at scale, dramatically changes when fault-tolerant quantum computing becomes practically achievable by shrinking the total physical qubit count required for commercially useful computation.
The Loon Processor and the qLDPC Challenge
Bivariate bicycle codes impose a connectivity requirement that standard superconducting chip architectures cannot meet. While surface codes need only nearest-neighbor qubit connections, bivariate bicycle codes require degree-6 qubit connectivity, meaning each qubit must interact with up to six others, including non-nearest neighbors.
IBM built Loon, announced in late 2025, specifically to meet that requirement, incorporating several hardware innovations developed for this purpose:
- C-couplers: tunable couplers extended to lengths up to 16mm (with a design target of 20mm) that connect qubits at non-adjacent positions on the chip, enabling the long-range interactions required by bivariate bicycle codes
- Six-way qubit coupling: a central qubit connected via tunable couplers to six neighboring qubits, demonstrating low crosstalk and acceptable fidelity across all six connections simultaneously
- Multi-layer routing: additional wiring layers on the chip surface to accommodate increased connection density without the crosstalk penalties that would otherwise degrade error rates
- Fast qubit reset: rapid reset capability that returns qubits to the ground state, a prerequisite for fast syndrome measurement cycles
Alongside Loon, IBM achieved real-time qLDPC decoding latencies below 480 nanoseconds. This is a critical performance threshold, as quantum states degrade on microsecond timescales. Detecting and correcting an error before new errors accumulate requires decoding each syndrome cycle in under one microsecond.
IBM also introduced a novel FPGA-compatible decoder that delivers approximately 10x speedup over the leading prior approach, enabling the real-time decode-and-correct loop required for fault-tolerant computation.
IBM’s Modular Fault-Tolerant Roadmap
IBM’s roadmap toward fault-tolerant quantum computing follows a structured sequence of processors. Kookaburra, planned for 2026, targets the first implementation of a qLDPC memory module combined with a logical processing unit, capable of storing information in an error-corrected code and executing logical gate operations on that stored information.
Cockatoo, planned for 2027, will demonstrate entanglement between two Kookaburra modules using L-couplers, proving that the modular architecture can scale beyond a single chip.
IBM’s target system, Starling, planned for 2029, combines multiple modules with error-corrected memory, logical-gate capability, and a fast decoder to realize approximately 200 logical qubits that can execute 100 million gates.
IBM’s qLDPC approach reduces physical qubit overhead by up to 90% compared to surface code architectures while achieving comparable error-correction performance.
The 2026 milestones, including Kookaburra deployment and the first fault-tolerant module demonstration, will provide the first hardware-based validation of the qLDPC efficiency claims at operationally relevant scales.
What Solving Error Correction Means for Commercialization
Below-threshold operation on trapped-ion hardware and qLDPC hardware on superconducting systems have together moved fault-tolerant quantum computing from an open physics question to a well-defined engineering program. Substantial obstacles remain, but they are now those of building and scaling a known architecture rather than of discovering whether a workable architecture exists.
This distinction matters enormously for commercial planning horizons. Enterprises and government agencies building quantum computing strategies can now assess vendor roadmaps against concrete intermediate milestones such as logical qubit counts, circuit depths, and error rates per gate operation, rather than evaluating abstract claims about future hardware capabilities.
The Commercial Timeline
Riverlane‘s 2026 QEC Technology Roadmap describes the scaling trajectory in terms of reliable operation counts:
- MegaQuOp systems (one million reliable operations), achievable before the end of the decade under multiple roadmap projections, enable early scientific applications in chemistry and materials science that classical supercomputers cannot efficiently address.
- GigaQuOp systems (one billion reliable operations), expected in the early 2030s, open the first wave of commercial quantum applications at production scale.
IBM targets Starling with 100 million gate operations at 200 logical qubits by 2029, placing it at the boundary of that MegaQuOp threshold.
Quantinuum’s Helios and its successors, combined with Microsoft’s qubit-virtualization platform, target a parallel scaling path on trapped-ion hardware.
The applications that stand to benefit most from fault-tolerant quantum computing are those in which classical simulation scales exponentially with problem complexity. Pharmaceutical companies using molecular simulation for drug discovery, materials science organizations modeling battery chemistry or high-temperature superconductors, and financial institutions running large-scale optimization on correlated asset portfolios represent the early commercial addressable market.
Current NISQ-era hybrid algorithms already run on quantum hardware for some of these use cases, but error-corrected systems will increase the tractable problem size by orders of magnitude.
Cryptographic Implications
The commercialization narrative for QEC has a dual dimension that enterprise technology and security organizations cannot ignore. The same fault-tolerant systems that accelerate drug discovery also approach the threshold at which Shor’s algorithm can break RSA and elliptic-curve cryptography using commercially deployed key sizes.
A 2025 Google analysis reduced the estimated number of physical qubits required to break RSA-2048 from 20 million to under one million, driven by algorithmic improvements rather than hardware advances.
NIST finalized its first post-quantum cryptography standards in August 2024 and designated 2026 as a transition year. The G7 Cyber Expert Group adopted a post-quantum roadmap in January 2026, targeting financial-sector infrastructure.
Cryptographically relevant quantum computing remains years beyond current hardware capabilities. However, the trajectory established by 2024 through 2026 QEC milestones has materially shortened the planning horizon for cryptographic migration.
Organizations that treat post-quantum cryptography as a 2030s problem may find that the timeline has compressed.
What Remains Unsolved
The remaining challenges are engineering problems, but they are difficult ones. Physical qubit counts for fault-tolerant systems at useful scales still run into the thousands to millions, depending on code choice and target algorithm. Cryogenic infrastructure, control electronics, and fabrication yields must all scale alongside qubit counts.
The modular architectures that IBM and Quantinuum are pursuing introduce inter-module communication challenges, including transmitting quantum states between physically separate processors without introducing errors that overwhelm the correction capacity.
Real-time decoding at the speeds fault tolerance requires demands classical compute infrastructure capable of processing syndrome data at rates current hardware only approaches.
The overhead ratio between physical and logical qubits also remains the central economic constraint. IBM’s qLDPC approach targets a 10x improvement over surface codes, but sustaining that ratio as code distance and logical qubit counts increase requires experimental validation that the current roadmap has not yet provided.
Trapped-ion systems achieve high fidelity but face scaling challenges in qubit count that superconducting systems do not, while superconducting systems offer larger qubit counts but face fidelity challenges that trapped-ion systems have already overcome.
Final Thoughts
Quantum error correction has moved from theoretical possibility to experimental reality. The Microsoft-Quantinuum Nature publication and IBM’s Loon-based qLDPC architecture are the two most substantive advances in QEC, and they point toward fault-tolerant computing via different technical paths on different hardware platforms.
It’s an architectural diversity that strengthens the field. The two approaches do not compete directly so much as they validate different routes to the same destination, providing the industry with multiple paths through the remaining engineering challenges.
Commercial deployment of fault-tolerant quantum computing at utility scale remains a multi-year effort. IBM targets Starling in 2029; Quantinuum and Microsoft are advancing trapped-ion hardware to increase logical qubit counts under the Helios roadmap. Neither timeline guarantees delivery, and both organizations have previously extended their projections.
What distinguishes this moment from earlier phases in quantum computing is that execution failures now correspond to solvable engineering setbacks rather than to unknown physics.
For enterprise technology leaders, the near-term priority is not to wait for fault-tolerant quantum computing but to prepare for it. Evaluate hybrid quantum-classical workflows on current hardware, invest in quantum-ready algorithm development, and, critically, advance post-quantum cryptographic migration plans on a timeline that reflects a shortened threat horizon.
The era of logical qubits has begun. The commercialization calendar is now sufficiently defined to plan against.
